8259A Programmable Interrupt Controller || MicroProcessor

Introduction

The 8259 is a programmable interrupt managing device specially designed for use with the interrupt signals of the 8085 microprocessor.

The 8259A block diagram includes control logic, registers for interrupt requests, priority resolver, cascade logic and data bus. The registers manage interrupt requests, the priority resolver determine their priority. The cascade logic is used to connect additional 8259A devices

Operation of 8259A

The following steps take place during the operation of 8259A :

1. One or more interrupt request lines go high requesting the service. 2. The 8259A resolves the priorities and sends an INT signal to the microprocessor. 3. The microprocessor acknowledges the interrupt by sending INTA. 4. After the INTA has been received, the opcode for the call instruction (CDH) is placed on the data bus. 5. Because of the call instruction, the microprocessor sends two more INTA signals. 6. At the first INTA, 8259A places the low order 8-bit address on the data bus and at the second INTA, it places the higher order 8-bit address of the interrupt vector. This completes the 3 bytes CALL instruction. 7. The program sequence of the microprocessor is transferred to the memory location specified by the CALL instruction.